Sunday, December 5, 2010

Basics of VHDL...

Assalaamu Alaikum,

May peace and blessings of the Almighty be upon you and your family...aamin

VHDL stands for Very high speed integrated circuit Hardware Description Language. It contains two major parts, namely

1. Entity and
2. Architecture

Entity is the external view of the project. Here one needs to describe the external features of the project such as Inputs and Outputs.

Architecture is the internal view of the project. Here one needs to describe how those inputs and outputs are  internally connected.

For example, let us consider the below example of Half-Subtractor,

Let us see how to write VHDL code for the above project,


entity half_sub is
port (a,b : in bit; diff,bor : out bit);
end half_sub;

One can understand from the above code that entity contains inputs and outputs which are external to the project.

VHDL is a case insensitive language. Entity name can be of any name but care must be taken so that the entity name (here half_sub) should not start with numerics (eg. 24halfsub) and should not be the “keywords” such as xor, and, or, nand, nor, xnor etc.,


Architecture data of halfsub is
Signal s1:bit;

diff <= a xor b;
s1 <=  not a;
bor <= s1 and b;

end data;

As it is shown above, connection details of the inputs and outputs (which we defined in the entity ) are described in the architecture. Signal is the one which connects two gates and it should be defined between “architecture” and “begin”.

Being a beginner to VHDL one should have a clear vision about the distinction of entity and architecture as it is shown above.

Hope this helps the beginners.

May the Almighty keep us in the straight path always…

Thanks and Regards,
Aashiq Ahamed A